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data sheet 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 8v43fs92432 revision 1 10/28/15 1 ?2015 integrated device technology, inc. general description the 8v43fs92432 is a 3.3v-compatible, pll based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. with output frequencies from 21.25mhz to 1360mhz and the support of two differential pecl output signals, the device meets the needs of the most demanding clock applications. the 8v43fs92432 is a programmable high-frequency clock source (clock synthesizer). the internal pll generates a high-frequency output signal based on a low-frequency reference signal. the frequency of the output signal is programmable and can be changed on the fly for frequency margining purpose. the internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. alternatively, a lvcmos compatible clock signal can be used as a pll reference signal. the frequency of the internal crystal oscillator is divided by a selectable divider and then multiplied by the pll. its output is scaled by a divider that is configured by either the i 2 c or parallel interfaces. the crystal oscillator frequency f xtal, the pll pre-divider p, the feedback-divider m, and the pll post-divider n determine the output frequency. the feedback path of the pll is internal. the pll post-divider n is conf igured through either the i 2 c or the parallel interfaces, and can provide one of six division ratios (2, 4, 8, 16, 32, 64). this divider extends the performance of the part while providing a 50% duty cycle. th e high-frequency outputs, q a and q b , are differential and are capable of driving a pair of transmission lines terminated 50 ? to v cc ? 2.0 v. the second high-frequency output, q b , can be configured to run at either 1x or 1/2x of the clock frequency or the first output (q a ). the positive supply voltage for the internal pll is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. the configuration logic has two sections: i 2 c and parallel. the parallel interface uses the values at the m[9:0], na[2:0], nb, and p parallel inputs to configure the internal pll dividers. the parallel programming interface has priority over the serial i 2 c interface. the serial interface is i 2 c compatible and provides read and write access to the internal pll configuration re gisters. the lock state of the pll is indicated by the lvcmos-compatible lock output. features ? 21.25mhz to 1360mhz synthesized clock output signal ? two differential, lvpecl-compatible high-frequency outputs ? output frequency programmable through 2-wire i 2 c bus or parallel interface ? on-chip crystal oscillator for reference frequency generation ? alternative lvcmos compatible reference clock input ? synchronous clock stop functionality for both outputs ? lock indicator output (lvcmos) ? lvcmos compatible control inputs ? fully integrated pll ? 3.3-v power supply ? 48-lead lqfp ? 48-lead pb-free package available ? sige technology ? ambient temperature range: ?40c to +85c applications ? programmable clock source for server, computing, and telecommunication systems ? frequency margining ? oscillator replacement
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 2 revision 1 10/28/15 block diagram p osc pll nb na m f ref f vco f qa f qb ref_clk xtal1 xtal2 ref_sel test_en sda scl adr[1:0] pload m[9:0] na[2:0] nb p clk_stopx bypass mr qa qb lock pll configuration registers i 2 c control npload nmr nbypass nclk_stop[a:b] pin assignment 48-pin, 7mm x 7mm lqfp package scl nmr v cc npload na0 na1 na2 gnd adr0 adr1 sda p m2 m4 gnd m5 m6 m7 m8 m9 m0 m1 m3 v cc v cc nbypass gnd v cc v cc_pll ref_sel ref_clk gnd nclk_stopa nclk_stopb xtal1 xtal2 v cc nb v cc qa nqa gnd v cc qb nqb gnd lock test_en 123456789101112 24 23 22 21 20 19 18 16 17 15 14 13 37 38 39 40 41 42 43 45 44 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 it is recommended to use an external rc filter for the analog v cc_pll supply pin. please see the appl ication section for details.
revision 1 10/28/15 3 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet pin description and characteristic tables table 1. pin description table number name type 1 description 1v cc power positive supply for i/o and core. 2 nbypass input pullup selects the static circuit bypass mode. 3 gnd power power supply ground. 4v cc power positive supply for i/o and core. 5v cc_pll power positive power supply for the pll (anal og power supply). it is recommended to use an external rc filter fo r the analog power supply pin v cc_pll. 6 ref_sel input pullup selects the reference clock input. 7 ref_clk input pulldown pll external single-ended re ference input. lvcmos/lvttl interface levels. 8 gnd power power supply ground. 9 nclk_stopa input pullup output qx disable in logic low state. 10 nclk_stopb input pullup output qx disable in logic low state. 11 xtal1 crystal input crystal input. 12 xtal2 crystal output crystal output. 13 v cc power positive supply for i/o and core. 14 m0 input pulldown pll feedback divider configuration. 15 m1 input pulldown pll feedback divider configuration. 16 m2 input pullup pll feedback divider configuration. 17 m3 input pulldown pll feedback divider configuration. 18 m4 input pullup pll feedback divider configuration. 19 gnd power power supply ground. 20 m5 input pullup pll feedback divider configuration. 21 m6 input pullup pll feedback divider configuration. 22 m7 input pullup pll feedback divider configuration. 23 m8 input pullup pll feedback divider configuration. 24 m9 input pulldown pll feedback divider configuration. 25 test_en input pulldown factory test mode enable. this input must be set to logic low level in all applications of the device. 26 lock output lvcmos pll lock indicator. 27 gnd power power supply ground. 28 nqb output lvpecl high frequency clock output. 29 qb output lvpecl high frequency clock output. 30 v cc power positive supply for i/o and core. 31 gnd power power supply ground. 32 nqa output lvpecl high frequency clock output. 33 qa output lvpecl high frequency clock output.
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 4 revision 1 10/28/15 34 v cc power positive supply for i/o and core. 35 nb input pulldown pll post-divider configuration for output qb. 36 v cc power positive supply for i/o and core. 37 gnd power power supply ground. 38 na2 input pulldown pll post-divider configuration for output qa. 39 na1 input pullup pll post-divider configuration for output qa. 40 na0 input pulldown pll post-divider configuration for output qa. 41 npload input pulldown selects the programming interface. 42 v cc power positive supply for i/o and core. 43 nmr input pullup device master reset. 44 sda i/o pullup i 2 c data. 45 scl input pullup i 2 c clock. 46 adr1 input pulldown selectable two bits of the i 2 c slave address. 47 adr0 input pulldown selectable two bits of the i 2 c slave address. 48 p input pullup pll pre-divider configuration. note 1. pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics table symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2pf r pullup input pullup resistor 75 k ? r pulldown input pulldown resistor 75 k ? table 1. pin description table number name type 1 description
revision 1 10/28/15 5 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet table 3. function table control default 1 note 1. default states are set by internal input pull-up or pull-down resistors of 75k ?? 01 inputs ref_sel 1 selects ref_clk input as pll reference clock s elects the xtal interface as pll reference clock m[9:0] 01 1111 0100b 2 note 2. if f ref = 16mhz, the default configuration will re sult in a output frequency of 250mhz. pll feedback divider (10-bit) parallel programming interface na[2:0] 010 pll post-divider parallel programming interface. see table 10 nb 0 pll post-divider parallel programming interface. see table 11 p 1 pll pre-divider parallel programming interface. see table 9 npload 0 selects the parallel programming interface. the internal pll divider settings (m, na, nb and p) are equal to the setting of the hardware pins. leaving the m, na, nb and p pins open (floating) results in a default pll configuration with f out = 250mhz. see application/programming section. selects the serial (i 2 c) programming interface. the internal pll divider settings (m, na, nb and p) are set and read through the serial interface. adr[1:0] 00 address bit = 0 address bit = 1 sda, scl see programming the 8v43fs92432 nbypass 1 pll function bypassed f qa = f ref n a and f qb = f ref (n a n b ) pll function enabled: f qa = (f ref p) m n a and f qb = (f ref p) m (n a n b ) test_en 0 application mode. test mode disabled. factory test mode is enabled nclk_stop[a:b] 1 output q x is disabled in logic low state. synchronous disable is only guaranteed if nb = 0. output q x is synchronously enabled nmr the device is reset. the output frequency is zero and the outputs are asynchronously forced to logic low state. after releasing reset (upon the rising edge of nmr and independent on the state of npload), the 8v43fs92432 reads the parallel interface (m, na, nb and p) to acquire a valid startup frequency configuration. see application/programming section. the pll attempts to lock to the reference signal. the t lock specification applies. outputs lock pll is not locked pll is frequency locked
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 6 revision 1 10/28/15 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. condition table 4. absolute maximum ratings symbol characteristics min max unit v cc supply voltage -0.3 3.6 v v in dc input voltage -0.3 v cc + 0.3 v v i crystal input voltage 0 2 v v out dc output voltage -0.3 v cc + 0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature -65 125 c t func functional temperature range t a = -40 t a = +85 c t j operating junction temperature 125 c hbm esd human body model 1 note 1. according to jedec/js-001-2012/jesd22-c101e. 2000 v cdm esd charged device model 1 500 v
revision 1 10/28/15 7 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet table 5. dc ch aracteristics, v cc = 3.3 v 5%, gnd = 0v, t j = ?40c to +85c symbol parameter condition mi nimum typical maximum unit lvcmos control inputs (m[9:0], n[2:0] , addr[1:0], nb, p, nclk_stop[a:b], nbypa ss, nmr, ref_sel, test_en, npload) v ih input high voltage lvcmos 2.0 v cc + 0.3 v v il input low voltage lvcmos 0.8 v i in input current 1 note 1. inputs have pull-down resi stors affecting the input current. v in = v cc or gnd 200 a i 2 c inputs (scl, sda) v ih input high voltage lvcmos 2.0 v cc + 0.3 v v il input low voltage lvcmos 0.8 v i in input current v in = v cc 10 a v in = gnd -150 a lvcmos output (lock) v oh output high voltage i oh = ?4ma 2.4 v v ol output low voltage i ol = 4ma 0.4 v i 2 c open drain output (sda) v ol input low voltage i ol = 4ma 0.4 v differential clock output qa, qb 2 note 2. outputs terminated 50 ? to v tt = v cc ? 2v. v oh output high voltage lvpecl v cc ? 1.02 v cc ? 0.74 v v ol output low voltage lvpecl v cc ? 1.95 v cc ? 1.5 v v o(p-p) output peak-to-peak voltage 0.5 1.0 v supply current i cc_pll pll supply current v cc_pll pins, output unloaded 27 ma i cc power supply current all v cc pins, output unloaded 138 ma table 6. crystal characteristics parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 15 20 mhz equivalent series resistance (esr) 50 ? shunt capacitance 5 7 pf load capacitance (cl) 10 pf
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 8 revision 1 10/28/15 table 7. ac ch aracteristics, v cc = 3.3 v 5%, gnd = 0v, t j = ?40c to +85c) 1 2 symbol parameter condition minimum typical maximum unit f xtal crystal interface frequency range 15 16 20 mhz f ref fref_ext ? reference frequency range 15 20 mhz f vco vco frequency range 3 1360 2720 mhz f out output frequency 4 n = 2 680 1360 mhz n = 4 340 680 mhz n = 8 170 340 mhz n = 16 85 170 mhz n = 32 42.5 85 mhz n = 64 21.25 42.5 mhz f scl serial interface (i 2 c) clock frequency 0 0.4 mhz t p,min minimum pulse width (npload) 50 ns dc output duty cycle 5 45 50 55 % t sk(o) output-to-output skew 5 nb = 0 (f qa = f qb )38ps nb = 1 (f qa = 2 f qb )96ps t r , t f output rise/fall time (qa, qb) 5 20% to 80% 0.05 0.3 ns t r , t f output rise/fall time (sda) c l = 400pf 250 ns t p_en output enable time ? (nclk_stop[a:b] to qa, qb) t qx = output period 3.0 t qx ns t p_dis output disable time (nclk_stop[a:b] to qa, qb) t qx = output period 3.0 t qx ns t jit(cc) cycle-to-cycle jitter (rms 1 ? ) 6 nb = 0 ? (f_qa = f_qb) n = 2 27 ps n = 4 23 ps n = 8 21 ps n = 16 28 ps n = 32 32 ps n = 64 42 ps nb = 1 ? (f_qa = 2 * f_qb) n = 2 51 ps n = 4 38 ps n = 8 41 ps n = 16 44 ps n = 32 50 ps n = 64 57 ps n = 128, qb only 49 ps
revision 1 10/28/15 9 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet t jit(per) period jitter (rms 1 ? ) 7 nb = 0 ? (f_qa = f_qb) n = 2 6 ps n = 4 5 ps n = 8 4 ps n = 16 5 ps n = 32 6 ps n = 64 8 ps nb = 1 ? (f_qa = 2 * f_qb) n = 2 16 ps n = 4 12 ps n = 8 14 ps n = 16 12 ps n = 32 12 ps n = 64 14 ps n = 128, qb only 13 ps bw pll closed loop bandwidth 8 p = 2 150 khz p = 4 100 khz t lock maximum pll lock time 10 ms note 1. ac characteristics apply for parallel output termination of 50 ? to v tt = v cc ? 2v. note 2. electrical parameters are guarante ed over the specified ambient operating tem perature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 3. the input frequency f xtal , the pll divider m and p must match the vco frequency range: f vco = f xtal m p. the feedback divider m is limited to 170 ? m ? 340 (for p = 2) and 340 ? m ? 680 (for p = 4) for stable pll operation. note 4. output frequency for q a , q b if n b = 0. with n b = 1 the q b output frequency is half of the q a output frequency. note 5. unless specify otherwise, electric al characterization is performed with the bel ow output frequencies: 21.875, 30.626, 3 9.375, 45, 62.5, 80, 92.5, 127.5, 162. 5, 190, 260, 330, 390, 530, 670 800, 1080, 1360mhz and f ref = 16mhz. note 6. maximum cycle jitter meas ured at the lowest vco frequency. note 7. maximum cycle period measured at the lowest vco frequency. note 8. ?3 db point of pll transfer characteristics. table 7. ac ch aracteristics, v cc = 3.3 v 5%, gnd = 0v, t j = ?40c to +85c) 1 2 symbol parameter condition minimum typical maximum unit
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 10 revision 1 10/28/15 output frequency configuration the 8v43fs92432 is a programmable frequency source (synthesizer) and supports an output frequency range of ? 21.25mhz ? 1360mhz. the output frequency f out is a function of the reference frequency f ref and the three internal pll dividers p, m, and n. f out can be represented by this formula: f out = (f ref p) m (n a , b )(1) the m, n and p dividers require a configuration by the user to achieve the desired output frequency. the output divider, n a determines the achievable output frequency range (see ta b l e 8 ). the pll feedback-divider m is the frequency mu ltiplication factor and the main variable for frequency synthesis. for a given reference frequency f ref , the pll feedback-divider m must be configured to match the specified vco frequency range in order to achieve a valid pll configuration: f vco = (f ref p) m and (2) 1360 ? ? f vco ? ? ? 2720 (3) the output frequency may be changed at any time by changing the value of the pll feedback divider m. the smallest possible output frequency change is the synthesizer granularity g (difference in f out when incrementing or decrement ing m). at a given reference frequency, g is a function of the p ll pre-divider p and post-divider n: g = f ref (p n a,b )(4) the n b divider configuration dete rmines if the output q b generates a 1:1 or 2:1 frequency copy of the q a output signal. the purpose of the pll pre-divider p is to situated the pll into the specified vco frequency range f vco (in combination with m). for a given output frequency, p = 4 results in a sma ller output frequency granularity g, p = 2 results a larger output frequency granularity g and also increases the pll bandwidth compared to the p = 2 setting. the following example illustrates t he output frequency range of the 8v43fs92432 using a 16mhz reference frequency. example output freq uency configuration if a reference frequency of 16mhz is available, an output frequency at q a of 250mhz and a small frequency granularity is desired, the following steps would be taken to identify the appropriate p, m, and n configuration: 1. use ta bl e 8 to select the output divider, n a , that matches the desired output frequency or frequency range. according to ta bl e 8 , a target output frequency of 250mhz falls in the f out range of 170mhz ? 340mhz and requires to set n a = 8. 2. calculate the vco frequency f vco = f out n a , which is 2000mhz in this example. 3. determine the pll feedback divider: m = f vco p. ? the smallest possible output granularity in this example calculation is 500khz (set p = 4). m calculates to a value of 2000 4 = 500. 4. configure the 8v43fs92432 with the obtained settings: m[9:0] = 0111110100b(binary number for m = 500) n a [2:0] = 010(8 divider, see ta b l e 10 ) p = 1 (4 divider, see ta b l e 9 ) n b = 0 (f out, qb = f out, qa ) 5. use either parallel or serial interface to apply the setting. the i 2 c configuration byte for this examples are: pll_h = 01010010b and pll_l = 11110100b. see ta bl e 15 and ta bl e 16 for register maps. pll divider configuration table 8. frequency ranges (f ref = 16 mhz) f out (q a ) [mhz] n a m p g [mhz] 680 ? 1360 n a = 2 170 ? 340 2 4 340 ? 680 4 2 340 ? 680 n a = 4 170 ? 340 2 2 340 ? 680 4 1 170 ? 340 n a = 8 170 ? 340 2 1 340 ? 680 4 0.5 85 ? 170 n a = 16 170 ? 340 2 0.5 340 ? 680 4 0.25 42.5 ? 85 n a = 32 170 ? 340 2 0.25 340 ? 680 4 0.125 21.25 ? 42.5 n a = 64 170 ? 340 2 0.125 340 ? 680 4 0.0625 table 9. pre-pll divider p pvalue 0f ref 2 1f ref 4 table 10. post-pll divider n a n a0 n a1 n a2 f out (q a ) 000f vco 2 001f vco 4 010f vco 8 011f vco 16 100f vco 32 101f vco 64 table 11. post-pll divider n b n b value 0f out, qb = f out, qa 1f out, qb = f out, qa 2
revision 1 10/28/15 11 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet programming th e 8v43fs92432 the 8v43fs92432 has a parallel and a serial configuration interface. the purpose of the parallel interface is to directly configure the pll dividers through hardware pins without the overhead of a serial protocol. at device startup, the device always obtains an initial pll frequency configuration through the parallel interface. the parallel interface does not support reading the pll configuration. the serial interface is i 2 c compatible. it allows reading and writing devices settings by accessing intern al device registers. the serial interface is designed for host-controller access to the synthesizer frequency settings for instance in frequency-margining applications. using the parallel interface the parallel interface supports write-access to the pll frequency setting directly through 15 configur ation pins (p, m[9:0], na[2:0], and nb). the parallel interface must be enabled by setting npload to logic low level. during npload = 0, any change of the logical state of the p, m[9:0], na[2:0], and nb pins will immediately affect the internal pll divider settings, resulting in a change of the internal vco-frequency and the output frequency. the parallel interface mode disables the i 2 c write-access to the internal registers; however, i 2 c read-access to the internal configuration registers is enabled. upon startup, when the device reset signal is released (rising edge of the nmr signal), the device read s its startup configuration through the parallel interface and independent on the state of npload. it is recommended to provide a valid pll configuration for startup. if the parallel interface pins are left open, a default pll configuration will be loaded. after the low-to-hi gh transition of npload, the configuration pins have no more effect and the configuration registers are made accessible through the serial interface. using the i 2 c interface npload = 1 enables the programming and monitoring of the internal registers through the i 2 c interface. device register access (write and read) is possible through the 2-wire interface using sda (configuration data) and scl (conf iguration clock) signals. the 8v43fs92432 acts as a slave device at the i 2 c bus. for further information on i 2 c it is recommended to refer to the i 2 c bus specification (version 2.1). npload = 0 disables the i 2 c-write-access to the configuration registers and any data written into the register is ignored. however, the 8v43fs92432 is still visible at the i 2 c interface and i 2 c transfers are acknowledged by the device. read-access to the internal registers during npload = 0 (parallel programming mode) is supported. note that the device automatically obtains a configuration using the parallel interface upon the release of the device reset (rising edge of nmr) and independent on the stat e of npload. changing the state of the npload input is not suppor ted when the device performs any transactions on the i 2 c interface. programming model and register set the synthesizer contains two fully accessible configuration registers (pll_l and pll_h) and a write-only command register (cmd). programming the synthesizer frequency through the i 2 c interface requires two steps: 1) writing a valid pll configuration to the configuration registers and 2) loading the registers into the pll by an i 2 c command. the pll frequency is affected as a result of the second step. this two-step procedure can be performed by a single i 2 c transaction or by multiple, independent i 2 c transactions. an alternative way to achieve small pll frequency changes is to use the increment or decrement comm ands of the synthesizer, which have an immediate effect on the pll frequency. figure 1. . i 2 c mode register set figure 1. illustrates the synthesizer register set. pll_l and pll_h store a pll configuration and are fully accessible (read/write) by the i 2 c bus. cmd (write only) accepts commands (load, get, inc, dec) to update registers and for direct pll frequency changes. set the synthesizer frequency: 1) write the pll_l and pll_h registers with a new configura - tion (see ta bl e 15 and ta bl e 16 for register maps) 2) write the load command to update the pll dividers by the current pll_l, pll_h content. read the synthesizer frequency: 1) write the get commands to update the pll_l, pll_h reg - isters by the pll divider setting 2) read the pll_l, pll_h registers through i 2 c change the synthesizer frequency in small steps: 1) write the inc or dec comm and to change the pll frequen - cy immediately. repeat at any time if desired. table 12. pll feedback-di vider configuration (m) feedback divider m9876543210 pin m9m8m7m6m5m4m3m2m1m0 default 0111110100 table 13. pll pre/post-div ider configuration (n, p) post-div na 210 post-div nb nb pre-div pp pin na2 na1 na0 pin nb pin p default 0 1 0 default 0 default 1 configuration latches i 2 c registers i 2 c access synthesizer ? pll pn m load/get pll_l (r/w) 0x00 pll_h (r/w) 0x01 cmd (w) 0xf0
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 12 revision 1 10/28/15 load and get are inverse command to each other. load updates the pll dividers and get updates the configuration registers. a fast and convenient way to change the pll frequency is to use the inc (increment m) and dec (decrement m) commands of the synthesizer. inc (dec) directly increments (decrements) the pll-feedback divider m and immediately changes the pll frequency by the smallest step g (see ta b l e 8 for the frequency granularity g). the inc and dec commands are designed for multiple and rapid pll frequency changes as required in frequency margining applications. inc and dec do not require the user to update the pll dividers by the load command, inc and dec do not update the pll_l and pll_h registers either (use load for an initial pll divider setting and, if desired, use get to read the pll configuration). note that the synthesizer does not check any boundary conditions such as the vco frequency range. applying the inc and dec commands could result in invalid vco frequencies (vco frequency beyond lock range). register maps register 0x00 (pll_l) contains the least significant bits of the pll feedback divider m. register content: m[7:0] pll feedback-divider m, bits [7?0] register 0x01 (pll_h) contains the two most significant bits of the pll feedback divider m, four bits to control the pll post-dividers n and the pll pre-divider p. the bit 0 in pll_h register indicates the lock condition of the pll and is set by the synthesizer automatically. the lock state is a copy of the pll lock signal output (lock). a write-access to lock has no effect. register content: m[9:8] pll feedback-divider m, bits 9?8 ? na[2:0] pll post-divider n a , see ta b l e 10 ? nb pll post-divider n b , see ta b l e 11 ? p pll pre-divider p, see ta b l e 9 ? lock copy of lock output signal (read-only) note that the load command is required to update the pll dividers by the content of both pll_l and pll_h registers. register 0xf0 (cmd) is a write-only command register. the purpose of cmd is to provide a fast way to increase or decrease the pll frequency and to update the registers. the register accepts four commands, inc (increment m) , dec (decrement m), load and get (update registers). it is recommended to write the inc, dec commands only after a valid pll configuration is achieved. inc and dec only affect the m-divider of the pll (pll feedback). applying inc and dec commands can result in a pll configuration beyond the specified lock range and the pll may loose lock. the 8v43fs92432 does not verify the va lidity of any commands such as load, inc, and dec. the inc and dec commands change the pll feedback divider without updating pll_l and pll_h. i 2 c ? register access in parallel mode the 8v43fs92432 supports the conf iguration of the synthesizer through the parallel interlace (npload = 0) and serial interface (npload = 1). register contents and the divider configurations are not changed when the user switches from parallel mode to serial mode. however, when switching from serial mode to parallel mode, the pll dividers immediately reflec t the logical state of the hardware pins m[9:0], na[2:0], nb, and p. applications using the parallel interf ace to obtain a pll configuration can use the serial interface to verify the divider settings. in parallel mode (npload = 0), the 8v43fs92432 allows read-access to pll_l and pll_h through i 2 c (if npload = 0, the current pll configuration is stored in pll_l, pll_h. the get command is not necessary and also not supported in parallel mode). after changing from parallel to serial mode (npload = 1), the last pll configuration is still stored in pl l_l, pll_h. the user now has full write and read access to both configuration registers through the i 2 c bus and can change the configuration at any time. table 14. configur ation registers address name content access 0x00 pll_l least significant 8 bits of m r/w 0x01 pll_h most significant 2 bits of m, p, n a , n b , and lock state r/w 0xf0 cmd command register (write only) w only table 15. pll_l (0x0 0, r/w) register bit 76543210 name m7 m6 m5 m4 m3 m2 m1 m0 table 16. pll_h (0x01, r/w) register bit 7654321 0 name m9 m8 na2 na1 na0 nb p lock table 17. cmd (0xf0): pl l command (write-only) command op-code description inc xxxx0001b (0x01) increase internal pll frequency m= m+1 dec xxxx0010b (0x02) decrease internal pll frequency m= m-1 load xxxx0100b (0x04) update the pll divider config. pll divider m, n, p= pll_l, pll_h get xxxx1000b (0x08) update the configuration registers pll_l, pll_h= pll divider m, n, p table 18. pll configuration in parallel and serial modes pll configuration parallel serial (registers pll_l, pll_h) m[9:0] set pins m9?m0 m[9:0] (r/w) na[2:0] set pins na2...na0 na[2:0] (r/w) nb set pin nb nb (r/w) p set pin p p (r/w) lock status lock pin 26 lock (read only)
revision 1 10/28/15 13 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet programming the i 2 c interface the 7-bit i 2 c slave address of the 8v43fs92432 synthesizer is a combination of a 5-bit fixed addresses and two variable bits which are set by the hardware pins adr[1:0]. bit 0 of the 8v43fs92432 slave address is used by the bus cont roller to select either the read or write mode0? indicates a transmission (i 2 c-write) to the 8v43fs92432 1? indicates a request for data (i 2 c-read) from the synthesizer. the hardware pins adr1 and adr0 and should be individually set by the user to avoid address conflicts of multiple 8v43fs92432 devices on the same i 2 c bus. write mode (r/w = 0) the configuration registers are written by the bus controller by the initiation of a write transfer with the 8v43fs92432 slave address (first byte), followed by the address of the configuration register (second byte: 0x00, 0x01 or 0xf0), and the configuration data byte (third byte). this transfer may be followed by writing more registers by sending the configuration register address followed by one data byte. each byte sent by the bus controller is acknowledged by the 8v43fs92432. the transfer ends by a stop bit sent by the bus controller. the number of conf iguration data bytes and the write sequence are not restricted. read mode (r/w = 1) the configuration registers are read by the bus controller by the initiation of a read transfer. the 8v43fs92432 supports read transfers immediately after the fi rst byte without a change in the transfer direction. immediately af ter the bus controller sends the slave address, the 8v43fs92432 acknowledges and then sends both configuration register pll_l an d pll_h (back-to-back) to the bus controller. the cmd register cannot be read. in order to read the two synthesizer registers and the cu rrent pll configuration setting, the user can 1) read pll_l, pll_h, write the get command (loads the current configuration into pll_l, pll_h) and read pll_l, pll_h again. note that the pll_l , pll_h registers and divider settings may not be equivalent after the following cases: a. writing the inc command b. writing the dec command c. writing pll_l, pll_h registers with a new configuration and not writing the load command. table 19. i 2 c slave address bit76543 2 1 0 value10110 pin adr1 pin adr0 r/w table 20. complete configurat ion register write transfer 1 bit 7 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit start slave address r/w ack &pll_h ack config- byte 1 ack &pll_l ack config-byte 2 ack stop 10110xx 1 note 1. xx = state of adr1, adr0 pins 0 0x01 data 0x00 data master master master slave master slave mast er slave master slave master slave master table 21. configuration register read transfer 1 bit 7 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit start slave address r/w ack pll_l ack pll_h ack stop 10110xx 1 note 1. xx = state of adr1, adr0 pins 1datadata master master master slave slave master slave master slave
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 14 revision 1 10/28/15 device startup general device configuration it is recommended to reset the 8v43fs92432 during or immediately after the system powers up (nmr = 0) . the device acquires an initial pll divider configuration through the parallel interface pins m[9:0], na[2:0], n, and p 1 with the low-to-high transition of nmr 2 . pll frequency lock is achieved within the specified lock time (t lock ) and is indicated by an assertion of the lock signal which completes the startup procedure. it is recommended to disable the outputs (nclk_stop[a:b] = 0) until pll lock is achieved to suppress output frequency transitions. t he output frequency can be reconfigured at any time through either the parallel or the serial interface. note that a pll configuration obtained by the parallel interface can be read through i 2 c independent on the current programming mode (parallel or serial). refer to i2c ? register access in parallel mode for additional information on how to read a pll startup configuration through the i 2 c interface. starting-up using the parallel interface the simplest way to use the 8v43fs92432 is through the parallel interface. the serial interface pi ns (sda, sdl, and addr[1:0]) can be left open and npload is set to logic low. after the release of nmr and at any other time the pll/ou tput frequency configuration is directly set to through the m[9:0], na[2:0], nb, and p pins. start-up using the serial (i 2 c) interface figure 2. start-up using i 2 c interface set npload = 1, nclk_stop[a:b] = l and leave the parallel interface pins (m[9:0], na[2:0], n, and p) open. the pll dividers are configured by the default configurat ion at the low-to-high transition of nmr. this initial pll configuration can be re-programmed to the final vco frequency at any time through the serial interface. after the pll achieved lock at the desired vco frequency, enable the outputs by setting nclk_stop[a:b] = h. pll lock and re-lock (after any configuration change through m or p) is indicated by lock being asserted. lock detect the lock detect circuitry indicates the frequency-lock status of the pll by setting and resetting the pin lock and register bit lock simultaneously. the lock status is asserted after the pll acquired frequency lock during the startup and is immediately de-asserted when the pll lost lock, for instance when the reference clock is removed. the pll may also loose lock when the pll feedback-divider m or pre-divider p is changed or the dec/inc command is issued. the pll may not loose lock as a result of slow reference frequency changes. in any case of loosing lock, the pll attempts to re-lock to the reference frequency. lock and re-lock of the pll is indicated by the lock signal after a delay of tbd cycles to prevent signaling temporary pll locks during frequency transitions. output clock stop asserting nclk_stop[a:b] will stop the respective output clock in logic low state. the nclk_stop[a:b] control is internally synchronized to the output clock signal, therefore, enabling and disabling outputs does not produce runt pulses. see figure 3. . the clock stop controls of the qa and qb outputs are independent on each other. if the qb runs at ha lf of the qa output frequency and both outputs are enabled at the same time, the first clock pulse of qa may not appear at the same time of the first qb output. (see figure 4. .) coincident rising edges of qa and qb stay synchronous after the assertion and de-assertion of the nclk_stop[a:b] controls. asserting nmr always resets the output divider to a logic low output state, with the risk of producing an output runt pulse. figure 3. clock stop timing for nb = 0 (f qa = f qb ) 1. the parallel interface pins m[9:0], na[2:0], n, and p may be left open (floating). in this case the initial pll configuration will have the default setting of ? v cc nmr p, m , n npload lock nclk_stop[a:b] qa, qb stable & valid selects i 2 c acquiring lock pll lock disabled (low) t plh active nclk_stop[a:b] qx (disable) (enable) (enable) t p_dis t p_en
revision 1 10/28/15 15 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet figure 4. clock stop timing for nb = 1 (f qa = 2 f qb ) frequency operating range nclk_stop[a:b] qa qb (disable) (enable) (enable) table 22. 8v43fs92432 frequen cy operating range for p = 2 f vco [mhz] (parameter: f ref in mhz) output frequency for f xtal = 16mhz (parameter n) mm[9:0] 15161820 2 4 8 16 32 64 170 0010101010 1360 1530 1700 680 340 170 85 42.50 21.25 180 0010110100 1440 1620 1800 720 360 180 90 45.00 22.50 190 0010111110 1425 1520 1710 1900 760 380 190 95 47.50 23.75 200 0011001000 1500 1600 1800 2000 800 400 200 100 50.00 25.00 210 0011010010 1575 1680 1890 2100 840 420 210 105 52.50 26.25 220 0011011100 1650 1760 1980 2200 880 440 220 110 55.00 27.50 230 0011100110 1725 1840 2070 2300 920 460 230 115 57.50 28.75 240 0011110000 1800 1920 2160 2400 960 480 240 120 60.00 30.00 250 0011111010 1875 2000 2250 2500 1000 500 250 125 62.50 31.25 260 0100000100 1950 2080 2340 2600 1040 520 260 130 65.00 32.50 270 0100001110 2025 2160 2430 2700 1080 540 270 135 67.50 33.75 280 0100011000 2100 2240 2520 1120 560 280 140 70.00 35.00 290 0100100010 2175 2320 2610 1160 580 290 145 72.50 36.25 300 0100101100 2250 2400 2700 1200 600 300 150 75.00 37.50 310 0100110110 2325 2480 1240 620 310 155 77.50 38.75 320 0101000000 2400 2560 1280 640 320 160 80.00 40.00 330 0101001010 2475 2640 1320 660 330 165 82.50 41.25 340 0101010100 2550 2720 1360 680 340 170 85.00 42.50
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 16 revision 1 10/28/15 table 23. 8v43fs92432 frequen cy operating range for p = 4 f vco [mhz] (parameter: f ref in mhz) output frequency for f xtal = 16 mhz (parameter n) m m[9:0] 15 16 18 20 2 4 8 16 32 64 340 0101010100 1360 1530 1700 680 340 170 85.0 42.50 21.25 350 0101011110 1400 1575 1750 700 350 175 87.5 43.75 21.875 360 0101101000 1440 1620 1800 720 360 180 90.0 45.00 22.50 370 0101110010 1387.5 1480 1665 1850 740 370 185 92.5 46.25 23.125 380 0101111100 1425.0 1520 1710 1900 760 380 190 95.0 47.50 23.75 390 0110000110 1462.5 1560 1755 1950 780 390 195 97.5 48.75 24.375 400 0110010000 1500.0 1600 1800 2000 800 400 200 100.0 50.00 25.00 410 0110110010 1537.5 1640 1845 2050 820 410 205 102.5 51.25 25.625 420 0110100100 1575.0 1680 1890 2100 840 420 210 105.0 52.50 26.25 430 0110101110 1612.5 1720 1935 2150 860 430 215 107.5 53.75 26.875 440 0110111000 1650.0 1760 1980 2200 880 440 220 110.0 55.00 27.50 450 0111000010 1687.5 1800 2025 2250 900 450 225 112.5 56.25 28.125 460 0111001100 1725.0 1840 2070 2300 920 460 230 115.0 57.50 28.75 470 0111010110 1762.5 1880 2115 2350 940 470 235 117.5 58.75 29.375 480 0111100000 1800.0 1920 2160 2400 960 480 240 120.0 60.00 30.00 490 0111101010 1837.5 1960 2205 2450 980 490 245 122.5 61.25 30.626 500 0111110100 1875.0 2000 2250 2500 1000 500 250 125.0 62.50 31.25 510 0111111110 1912.5 2040 2295 2550 1020 510 255 127.5 63.75 31.875 520 1000001000 1950.0 2080 2340 2600 1040 520 260 130.0 65.00 32.50 530 1000010010 1987.5 2120 2475 2650 1060 530 265 132.5 66.25 33.125 540 1000011100 2025.0 2160 2520 2700 1080 540 270 135.0 67.50 33.75 550 1000100110 2062.5 2200 2565 1100 550 285 137.5 68.75 34.375 560 1000110000 2100.0 2240 2610 1120 560 280 140.0 70.00 35.00 570 1000111010 2137.5 2280 2700 1140 570 285 142.5 71.25 35.625 580 1001000100 2175.0 2320 1160 580 290 145.0 72.50 36.25 590 1001001110 2212.5 2360 1180 590 295 147.5 73.75 36.875 600 1001011000 2250.0 2400 1200 600 300 150.0 75.00 37.50 610 1001100010 2287.5 2440 1220 610 305 152.5 76.25 38.125 620 1001101100 2325.0 2480 1240 620 310 155.0 77.50 38.75 630 1001110110 2362.5 2520 1260 630 315 157.5 78.75^ 39.375 640 1010000000 2400.0 2560 1280 640 320 160.0 80.00 40.00 650 1010001010 2437.5 2600 1300 650 325 162.5 81.25 40.625 660 1010010100 2475.0 2640 1320 660 330 165 82.5 41.25 670 1010011110 2512.5 2680 1340 670 335 167.5 83.75 41.875 680 1010101000 2550.0 2720 1360 680 340 170 85.00 42.50
revision 1 10/28/15 17 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet applications information recommendations for unused input and output pins i nputs: lvcmos control pins all control pins have internal pull up or pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal1 and xtal2 can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. outputs: lvpecl outputs all unused lvpecl outputs can be le ft floating. we recommend that there is no trace attached. both si des of the differential output pair should either be left floating or terminated.
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 18 revision 1 10/28/15 overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 5a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 5b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl terminati on with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 5a. general diagram for lvcmos driver to xtal input interface figure 5b. general diagram for lvpec l driver to xtal input interface v d d xta l _ out xta l _ i n r1 100 r2 100 zo = 50 ohm s r s ro zo = ro + rs c1 .1u f lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
revision 1 10/28/15 19 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 6a and figure 6b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 6a. 3.3v lvpecl output termination figure 6b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v + _
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 20 revision 1 10/28/15 schematic example figure 7 shows an example of 8v43fs92432 application schematic. in this example, the device is operated at v cc = vcc_pll = 3.3v. the schematic example focuses on fu nctional connections and is not configuration specific. refer to t he pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. a 12pf parallel resonant 20mhz crystal is used. for this device, the crystal load capacitors are required for proper operation. the load capacitance, c1 = c2 = 2pf, are recommended for frequency accuracy. depending on the variatio n of the parasitic stray capacity of the printed circuit board traces between the crystal and the xtal_in and xtal_out pins, the values of c1 and c2 might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specificat ions can be used, but this will require adjusting c1 and c2. when designing the circuit board, return the capacitors to ground though a single point contact close to the package. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requ ired. the 8v43fs92432 provides separate power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the f ilter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pi n filter should be placed on the device side. the other components can be on the opposite side of the pcb. power supply filter recomm endations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to attenuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.
revision 1 10/28/15 21 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet figure 7. signal i/o and power filters
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 22 revision 1 10/28/15 power considerations this section provides information on power dissipa tion and junction temperature for the 8v43fs92432. ? equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8v43fs92432 is the sum of the core power plus the power dissipated due to the load. ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? the maximum current is: i cc_max = 165ma ? power (core) max = v cc_max * i cc_max = 3.465v * 165ma = 571.7mw ? power (outputs) max = 33.65mw/loaded output pair ? if all outputs are loaded, the total power is 2 * 33.65mw = 67.3mw total power_ max (3.465v, with all outputs s witching) = 571.7mw + 67.3mw = 639mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ? ja must be used. assuming 1m/s air flow and a multi-layer board, the appropriate value is 60.4c/w per table 24 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.639w * 60.4c/w = 123.6c. this is within the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 24. thermal resistance ? ja for 48-lead lqfp, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 70.2c/w 60.4c/w 56.9c/w
revision 1 10/28/15 23 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 8 . figure 8. lvpecl driver circuit and termination to calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.74v ? (v cc_max ? v oh_max ) = 0.74v ? for logic low, v out = v ol_max = v cc_max ? 1.5v ? (v cc_max ? v ol_max ) = 1.5v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = ? [(2v ? 0.74v)/50 ? ] * 0.74v = 18.65mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = ? [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 33.65mw v out v cc v cc - 2v q1 rl 50
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 24 revision 1 10/28/15 reliability information transistor count the transistor count for 8v43fs92432 is: 12,972 table 25. ? ja vs. air flow table for a 48-lead lqfp ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 70.2c/w 60.4c/w 56.9c/w
revision 1 10/28/15 25 1360mhz dual output lvpecl clock synthesizer 8v43fs92432 data sheet package dimensions case 932-03 issue f 48-lead lqfp package notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. dimensioning and tolerancing per asme y14.5m, 1994. controlling dimension: millimeter. datum plan ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. datums t, u, and z to be determined at dataum plane ab. dimensions s and v to be determined at seating plane ac. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. minimum solder plate thickness shall be 0.0076. exact shape of each corner is optional. a a1 z 0.200 ab t-u 4x z 0.200 ac t-u 4x b b1 1 12 13 24 25 36 37 4 8 s1 s v v1 detail y 9 t u z p ae ae t, u, z detail y m? top & bottom l? w k aa e c h 0.250 r detail ad gauge plane ad g 0.080 ac ab ac base metal n j f d t- u m 0.080 z ac section ae-ae min 1.400 0.170 1.350 0.170 0.050 0.090 0.500 0.090 0? 0.150 max 1.600 0.270 1.450 0.230 0.150 0.200 0.700 0.160 7? 0.250 dim a a1 b b1 c d e f g h j k m n p l r s s1 v v1 w aa millimeters 7.000 bsc 3.500 bsc 7.000 bsc 3.500 bsc 0.500 bsc 12? ref 0.250 bsc 9.000 bsc 4.500 bsc 9.000 bsc 4.500 bsc 0.200 ref 1.000 ref
8v43fs92432 data sheet 1360mhz dual output lvpecl clock synthesizer 26 revision 1 10/28/15 ordering information table 24. ordering information part/order number marking package shipping packaging temperature 8v43fs92432prgi idt8v43fs92432prgi 48 lea d lqfp, lead-free tube ?40c to +85c 8V43FS92432PRGI8 idt8v43fs924 32prgi 48 lead lqfp, lead-free tape & reel ?40c to +85c
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